Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically configured (programmed) by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA. Some PLDs also support partial reconfiguration, i.e., loading a partial bitstream that can change the functionality of a portion of the PLD while other portions of the PLD continue to function.
One such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) A simplified diagram of the Virtex-II CLB is shown in FIG. 1.
As shown in FIG. 1, a Virtex-II CLB includes four similar slices S0–S3. Each slice includes two 4-input lookup tables (LUTs) 101, 102 that can be configured to operate in any of three modes: lookup table mode, in which the LUT can provide any function of up to four inputs; RAM mode, in which the LUT provides a single or dual-port RAM of 8 or 16 bits; or shift mode, in which the LUT functions as a shift register up to 16 bits deep.
When in RAM mode, the write process is controlled by control signal generator 105, which provides control signal CS (which in RAM mode is a write strobe signal) to the LUTs (101, 102). (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Control signal generator 105 derives control signal CS from the clock CLK and clock enable CE input signals to the CLB. The RAM input data is supplied to the DI input terminal of each LUT 101, 102 by direct input terminals RAM_DI_1 and RAM_DI_2 via multiplexers DM1, DM2, respectively. Multiplexers DM1, DM2 are controlled by configuration memory cells (not shown).
When in shift mode, the shift process is controlled by the same control signal CS, which in shift mode is a shift enable signal. The shift input data for LUT 101 is supplied to the DI input terminal of LUT 101 from CLB input terminal ShiftIn via multiplexer DM1. The shift data output for each LUT is supplied by dedicated shift output terminal SR15. The shift input data for LUT 102 is supplied to the DI input terminal of LUT 102 from the shift out terminal SR15 of LUT 101 via multiplexer DM2.
Each LUT 101, 102 output signal OUT is read from the location in the LUT memory cell array addressed by the 4 input signals IN1–IN4. LUT output signal OUT is provided to an associated multiplexer MUX1, MUX2, which in turn provides a data input to an associated 1-bit register 103, 104. Direct input terminals Reg_DI_1, Reg_DI_2 also drive multiplexers MUX1, MUX2, respectively, allowing independent signals to be loaded into the registers via these direct input terminals. Multiplexers MUX1 and MUX2 are controlled by configuration memory cells (not shown). Registers 103, 104 are controlled by the clock CLK and clock enable CE signals and by other memory control signals (not shown).
The Virtex-II CLB also includes carry logic associated with each LUT/register pair. The output terminal OUT of each LUT 101, 102 controls a carry multiplexer CM1, CM2, which passes one of an externally supplied signal CM_DI_1, CM_DI_2 and an associated carry-in signal CIInt, CarryIn to a next carry multiplexer in the chain.
FIG. 2 is a simplified diagram of a portion of the Virtex-II CLB of FIG. 1, showing only those elements used in known test processes for testing the input structures of the LUT 201. The diagram of FIG. 2 includes LUT 201 and register 203, coupled as shown in FIG. 1.
FIG. 3 shows how several copies of the circuit of FIG. 2 can be used to test a portion of the LUT input structures using known testing methods. A “pseudo shift register” is created using the LUTs and registers of the CLB, each stage of the pseudo shift register including one LUT and its associated register. For example, a first stage of the pseudo shift register includes LUT 201a and register 203a, a second stage includes LUT 201b and register 203b, and an nth stage includes LUT 201n and register 203n. The LUTs are configured to implement buffers or inverters. Each register captures the output signal OUT from its associated LUT, and passes the registered value to the next LUT in the chain at each enabled clock signal.
To perform the test, a shift data input signal Test_In is applied to one input terminal of LUT 201a. Register 203a is enabled by clock enable signal CE, and clocked by a clock signal CLK to latch the output from LUT 201a. With each subsequent clock edge, the signal passes through an additional stage of the pseudo shift register. After n active clock edges, the test output signal Test_Out appears at the output terminal of the nth register 203n. This value is compared to an expected value. If the value is correct, the LUT input paths, registers, and interconnect resources used in this particular implementation are assumed to be functional.
However, this test method has its drawbacks. For example, suppose each LUT has K input terminals. Suppose further that each input terminal includes a wide multiplexer that selects one of M input signals from the interconnect structure to provide to the LUT. Using known test methods, at least K×M (K times M) test patterns are needed to determine whether or not each LUT input is fault-free. For example, in a Virtex-II LUT, K is 4 and M is 36. Thus, 144 different test patterns are required to test the input structures of a Virtex-II LUT.
Clearly, testing a PLD can be much more time-consuming than testing a comparably-sized non-programmable device, because of the number of possible configurations for each LUT. In fact, testing a PLD can be so time-consuming that testing becomes a greater expense than the actual manufacturing costs of the device.
Therefore, it is desirable to provide circuit implementations and test methods that reduce the time required to test the various structures in PLD LUTs.
Further, the test methods described in connection with FIGS. 2 and 3 do not necessarily detect “stuck at” faults in the memory cells implementing the LUT. If a memory cell is “stuck at” (i.e., permanently storing) a value that is the same as the value expected by the test, the fault is not detected. Therefore, additional “stuck at” tests are required to check for this type of defect.
Hence, it is further desirable to provide circuit implementations and test methods that can simultaneously test the input structures and the memory cells of a LUT, thereby reducing the test time and thus the final cost of the PLD.